Question about memory addressing

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Wickeycolumbus
Posts: 1
Joined: November 7th, 2013, 05:46

Question about memory addressing

Post by Wickeycolumbus » November 7th, 2013, 05:59

Hi there! I've been interested in the PM for quite a lot of time, finally joining this site.

I'm trying to get a picture of what is actually happening when memory is accessed on the PM. Looking through some of the info on the wiki, it appears that there are 10 address lines and 2 latch lines. Also, the cycle counts for the various instructions that address memory are quite long, in the 12-20 cycle range.

Piecing together that info, it would seem that half of the address is put on the bus, a latch line is clocked in some way, then the other half of the address is put on the bus and the opposite latch is clocked. Is this correct?

Does the processor physically only have 10 address pins and accesses all external memory in this fashion?

Are there any standard memory devices that use this addressing method?

JustBurn
Team Pokémé
Posts: 90
Joined: April 14th, 2011, 19:07

Re: Question about memory addressing

Post by JustBurn » November 9th, 2013, 06:08

It's only 2x 10-bits latches. Can't be simpler.

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